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Generating analog IC layouts with LAYGEN II [electronic resource] / Ricardo M. F. Martins, Nuno C. C. Lourenço, Nuno C.G. Horta.

Martins, Ricardo. (Author). Lourenço, Nuno. (Added Author). Horta, Nuno C. G. (Added Author). Ebooks Corporation (Added Author).
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Electronic resources

Subject: Linear integrated circuits > Design and construction.

Record details

  • ISBN: 9783642331466 (electronic bk.)
  • ISBN: 3642331467 (electronic bk.)
  • Physical Description: 1 online resource.
  • Publisher: Berlin ; Springer, c2013.

Content descriptions

Bibliography, etc. Note: Includes bibliographical references.
Formatted Contents Note: Generating Analog IC Layouts with LAYGEN II; Preface; Contents; Abbreviations; 1 Introduction; Abstract; 1.1...Analog IC Design; 1.2...The Analog IC Design Automation Flow; 1.3...Analog IC Layout Automation; 1.4...Conclusions; References; 2 State of the Art on Analog Layout Automation; Abstract; 2.1...Placement; 2.1.1 Layout Constraints; 2.1.2 Chip Floorplan Representations; 2.1.3 Approaches; 2.2...Layout Generation Tools; 2.3...Closing the Gap Between Electrical and Physical Design; 2.3.1 Layout-Aware Sizing Approaches; 2.4...Commercial Tools; 2.5...Conclusions; References; 3 Automatic Layout Generation
Abstract3.1...Design Flow Based on Automatic Generation; 3.1.1 Sizing Task; 3.2...Layout Generation Design Flow; 3.3...Tool Architecture; 3.3.1 Graphical User Interface; 3.3.2 Technology Design Kit; 3.3.3 Hierarchical High Level Cell Description; 3.4...Conclusions; References; 4 Placer; Abstract; 4.1...Placer Architecture; 4.2...Template; 4.3...Template-Based Generation Procedure; 4.3.1 Instantiation; 4.3.2 Pre-Processing; Biasing; Abutment; 4.3.3 Post-Processing; Minimum Distances; Guard Ring; 4.4...Conclusions; References; 5 Router; Abstract; 5.1...Router Architecture
5.2...Template5.3...Optimization-Based Generation Procedure; 5.3.1 Multiple Contacts; 5.3.2 Evolutionary Algorithm; Chromosome; Initialization; Genetic Operator: Crossover; Genetic Operator: Mutation; 5.3.3 Optimization Phases; 5.4...Internal Evaluation Procedure; 5.4.1 Short Circuit Checker; 5.4.2 Design Rule Checker; 5.4.3 Electrical Rule Checker; 5.5...Conclusions; References; 6 Results; Abstract; 6.1...Case Study I: Fully-Dynamic Comparator; 6.1.1 Template; 6.1.2 Layout Generation; Placer; Router; 6.1.3 Validation
6.2...Case Study II: Single-Ended Folded Cascode Amplifier6.2.1 Template Hierarchy; 6.2.2 Layout Generation; 6.2.3 Retargeting for Different Sizes; 6.2.4 Retargeting for Different Technology; 6.3...Conclusions; References; 7 Conclusions and Future Work; Abstract; 7.1...Conclusions; 7.2...Future Work; References
Reproduction Note: Electronic reproduction. Perth, W.A. Available via World Wide Web.
Source of Description Note: Description based upon print version of record.
◄ Search Results Showing Item 9 of 259

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